The following table summarizes the operational characteristics of my 4-bit experimental processor:
| Data bus | 4 bits |
| Address bus | 8 bits |
| Memory | 256 4-bit word |
| Accumulator | 8 bits |
| Program counter | 8 bits |
| Data address register (internal) | 8 bits |
| Instruction register (internal) | 4 bits |
| Flags | Carry, Zero, Data (external I/O) |
| Instruction set | 16 variable length instructions |
The 16 machine instructions are as follows:
| Opcode | Mnemonic | Size | Description |
| 0 | HLT | 1 | Halts the processor. Can be restarted manually by pressing a button. |
| 1 | LDA nn | 3 | Load 8-bit value from address nn into AC |
| 2 | STA nn | 3 | Store AC at address nn. |
| 3 | JMP nn | 3 | Continue execution at (i.e., set PC to) address nn. |
| 4 | SPC nn | 3 | Store current PC value at address nn. |
| 5 | AND nn | 3 | Compute logical AND of AC and nn, store result in AC. Set Z flag as appropriate. |
| 6 | OR nn | 3 | Compute logical OR of AC and nn, store result in AC. Set Z flag as appropriate. |
| 7 | ADD nn | 3 | Compute arithmetic sum of AC and nn, store result in AC. Set C and Z flags as appropriate. |
| 8 | SUB nn | 3 | Subtract nn from AC, store result in AC. Set C and Z flags as appropriate. |
| 9 | JNZ nn | 3 | Jump conditional; execute JMP nn if Z flag is not set. |
| A | CMP nn | 3 | Subtract nn from AC, discard result. Set C and Z flags as appropriate. |
| B | JND nn | 3 | Jump conditional; execute JMP nn if D flag is not set. |
| C | JNC nn | 3 | Jump conditional; execute JMP nn if C flag is not set. |
| D | ROL | 1 | Rotate AC left. Move C to least significant bit of AC. Move most significant bit to C. |
| E | ROR | 1 | Rotate AC right. Move C to most significant bit of AC. Move least significant bit to C. |
| F | CLF | 1 | Clear flags C, D, and Z. |
The LDA, STA, and SPC instructions are the only instructions that can read, or store, data at arbitrary memory locations. These instructions always operate on two 4-bit machine words at a time.
Other instructions use immediate arguments. That is, the instruction argument consists of two 4-bit words immediately following the single 4-bit instruction word.
This instruction set is obviously Spartan, but it is sufficient to implement any algorithm, memory size permitting. Restricting the instruction set to 16 instructions also greatly simplified design, since there's no need to fetch, and decode, instructions that consist of more than one 4-bit machine word.
